EEE 526: Assignment 2
1. Compute the critical path time of the HR filter circuit shown below. Assume that addition and multiplication take 1 u.t. and 2 u.t., respectively. Redistribute the delays to achieve a critical path
2. Consider the HR filter with y(n) = x(n) + ax(n 1) -f by(n – 2). What is the iteration period if the multiplier delay is 10ns and the adder delay is 2ns? Pipeline the filter so that it can be clocked at (i) 6ns, (ii) 3ns.
3. Consider the IIR filter //(z) = _0 25g 1»)(1 )’ ? Pipeline the filter so that each multiply-
add can be pipelined to 2 stages. Draw the complete structure with latches in appropriate locations.
4. Consider a first order IIR filter with transfer function 1/(1 – az~l). Implement this filter with a sample period of one-fourth multiply-add time by (i) 4-stage pipelining, andM-stage block processing (incremental) with block size of 4. What are the advantages/disadvantages of the two implementations.
5. Design a 3-stage systolic array system which computes Z ABCx as shown in the figure below. Here A, B and C are N x N matrices and x is an N x 1 vector. What should be the data flow such that the three stages are I/O matched, i.c. additional buffers are not require^between stages?
